1. Field of the Invention
This invention relates to a semiconductor device, especially to a DMOS (diffused MOS) type transistor.
2. Description of the Related Art
A DMOS type high withstand voltage MOS transistor has a high source-drain breakdown voltage or a high gate breakdown voltage. It has been broadly used in driver such as LCD driver as well as in power source circuit. Especially, a MOS transistor with a high source-drain breakdown voltage (BVds) and a low on resistance has been sought after in recent years.
FIG. 8 is a cross-sectional view of a configuration with both an N channel type DMOS transistor 100 and a P channel type MOS transistor 101 on a same semiconductor substrate.
An N type epitaxial layer 103 is disposed on the surface of a P type semiconductor substrate 102. An N+ type buried layer 104 is formed at the interface between the epitaxial layer 103 and the semiconductor substrate 102. The epitaxial layer 103 is divided into a plurality of regions by an isolation layer 105 made of P type impurities. In this figure, the device has a first confined region 106 and a second confined region 107.
An upper isolation layer 105a and a lower isolation layer 105b are superimposed in the epitaxial layer 103, making one portion, the isolation layer 105. The upper isolation layer 105a is formed by diffusing P type impurities, such as boron, downward from above the epitaxial layer 103. The lower isolation layer 105b is formed by diffusing P type impurities, such as boron, upward from the bottom surface of the semiconductor substrate 102.
The DMOS transistor 100 is formed in the epitaxial layer 103 of the first confined region 106. A gate electrode 109 is disposed on the epitaxial layer 103 with a gate insulation layer 108 between them. A P type body layer 110 is formed on the surface of the epitaxial layer 103 and an N+ type source layer 111 is formed adjacent to one edge of the gate electrode 109 on the surface of the body layer 110. Also, an N+ type drain layer 112 is formed adjacent to the other edge of the gate electrode 109 on the surface of the epitaxial layer 103.
The surface region of the body layer 110 between the epitaxial layer 103 and the source layer 111 is a channel region CH. A P+ type potential fixation layer 113 for fixing the potential of the body layer 110 is formed right next to the source layer 111.
The P channel type MOS transistor 101 that is configured from a source layer 114 on the epitaxial layer 103, a drain layer 115, a gate electrode 117 formed on the epitaxial layer 103 with a gate insulation film 16 between them, is formed in the second confined region 107.
The technology related to this invention is published in Japanese Patent Application Publication No. 2004-039774.
The epitaxial layer 103 also functions as a drain region in the DMOS transistor 100 described above. That is, the drain layer 112 and the epitaxial layer 103 are set at the same potential. Therefore, there is a limitation to what element can be formed with the DMOS transistor 100 within single region confined by the isolation layer 105 described above. For example, it is not possible to form both the DMOS transistor 100 and a P channel type MOS transistor 101 within single confined region. It is not possible either to form the DMOS transistor 100 and the DMOS transistor of an opposite conductivity type (P channel type) in single confined region.
However, the intense miniaturization and the higher integration of semiconductor device has been sought after in recent years. For example, there are cases, where voltages used in one confined area differ from that of different confined region: 200 volts as a high power source voltage (Vdd1) and 190 volts as a low power source voltage (Vss1) are used in one confined region and 10 volts as a high power source voltage and 0 volt as a low power source voltage are used in another confined region. With the configuration of prior arts, a large number of confined regions need to be formed in these cases, leading to the enlarged chip area.